module lfsr#(N_BIT=8)(clk, reset, Q);
  parameter [(N_BIT-1):0] init_x=8'b10010001;
  input clk;
  input reset;
  output reg [(N_BIT-1):0] Q;
  reg S;
  always @ (posedge clk) begin
    if (reset || Q==0) Q <= init_x;
    else begin
      S <= (((Q[7]^Q[5])^Q[4])^Q[3])^1'b1;
      Q <= {S, Q[(N_BIT-1):1]};
    end
  end
endmodule
